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low power, 16/24-bit sigma-delta adc with low-noise in-amp and embedded reference preliminary technical data AD7792/ad7793 rev.prf 6/04. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features resolution: AD7792: 16-bit ad7793: 24-bit low noise programmable gain instrumentation-amp rms noise: 80 nv (gain = 64) bandgap reference with 5ppm/ c drift typ power supply: 2.7 v to 5.25 v operation normal: 400 a typ power-down: 1 a max update rate: 4 hz to 500 hz simultaneous 50 hz/60 hz rejection internal clock oscillator programmable current sources (10 a/200 a/1 ma) on-chip bias voltage generator 100 na burnout currents independent interface power supply 16-lead tssop package interface 3-wire serial spi?, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications thermocouple measurements rtd measurements thermistor measurements functional block diagram gnd av dd AD7792/ad7793 serial interface and control logic internal clock clk sigma delta adc refin(+)/ain3(+) refin(-)/ain3(-) bandgap reference gnd in-amp v dd gnd dout/rdy din sclk cs dvdd ain1(+) ain1(-) ain2(+) ain2(-) v dd iout2 v bias iout1 mux figure 1. general description the AD7792/ad7793 is a low power, complete analog front end for low frequency measurement applications. the AD7792/ad7793 contains a low noise 16/24-bit -? adc with three differential analog inputs. the on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the adc. with a gain setting of 64, the rms noise is 80 nv when the update rate equals 16.6 hz. the device contains a precision low noise, low drift internal bandgap reference for absolute measurements. an external reference can also be used if ratiometric measurements are re- quired. on-chip programmable excitation current sources can be used to supply a constant current to rtds and thermistors while the 100 na burnout currents can be used to ensure that the sensors connected to the adc are not burnt out. for ther- mocouple applications, the on-chip bias voltage generator steps up the common mode voltage from the thermocouple so that it is within the adcs allowable range. the device can be operated with the internal clock or, alterna- tively, an external clock can be used if synchronizing several devices. the output data rate from the part is software pro- grammable and can be varied from 4 hz to 500 hz. the part operates with a power supply from 2.7 v to 5.25 v. it consumes a current of 450 ua maximum and is housed in a 16- lead tssop package.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 2 table of contents AD7792/ad7793?specifications.................................................. 3 timing characteristics , .................................................................... 6 absolute maximum ratings............................................................ 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 11 on-chip registers ........................................................................... 12 communications register (rs2, rs1, rs0 = 0, 0, 0) .............. 12 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x80 (AD7792) / 0x88 (ad7793)) ........................................... 13 mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a)........................................................................................ 13 configuration register (rs2, rs1, rs0 = 0, 1, 0; power- on/reset = 0x0710) .................................................................... 15 data register (rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x0000(00)) ................................................................................. 16 id register (rs2, rs1, rs0 = 1, 0, 0; power-on/reset = 0xxa (AD7792) / 0xxb (ad7793))........................................................ 16 io register (rs2, rs1, rs0 = 1, 0, 1; power-on/reset = 0x00) ....................................................................................................... 16 offset register (rs2, rs1, rs0 = 1, 1, 0; power-on/reset = 0x8000(AD7792)/ 0x800000(ad7793)).................................. 17 full-scale register (rs2, rs1, rs0 = 1, 1, 1; power- on/reset = 0x5xx5(AD7792)/ 0x5xxxx5(ad7793)) ............ 17 adc circuit information.............................................................. 19 overview ..................................................................................... 19 noise performance ..................................................................... 19 digital interface .......................................................................... 20 single conversion mode ....................................................... 21 continuous conversion mode............................................. 21 continuous read mode ........................................................ 22 circuit description......................................................................... 23 analog input channel ............................................................... 23 bipolar/unipolar configuration .............................................. 23 data output coding .................................................................. 23 reference ..................................................................................... 23 v dd monitor ................................................................................ 24 grounding and layout .............................................................. 24 outline dimensions ....................................................................... 26 esd caution................................................................................ 26 revision history rev.prf, june 2004: initial version
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 3 AD7792/ad7793?specifications 1 table 1. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v; all specifications t min to t max , unless otherwise noted.) parameter AD7792ad7793b unit test conditionscomments adc cannl spcification output update rate 4 min nom 500 ma nom adc cannl no missing codes 2 24 bits min f adc 125 . ad7793 16 bits min resolution (p p) 16 bits pp gain = 128, 16.6 update rate, v rf = 2.5v
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 4 parameter AD7792/ad7793b unit test conditions/comments @ 50 hz, 60 hz 2 100 db min 50 1 hz (fs[3:0] = 1001 6 ), 60 1 hz (fs[3:0] = 1000 6 ) reference internal reference initial accuracy 1.17 0.01% v min/max internal reference drift 5 ppm/c typ 15 ppm/c max internal reference noise 2 v rms gain = 1, update rate = 16.6 hz. includes adc noise. external refin voltage 2.5 v nom refin = refin(+) ? refin(?) reference voltage range 2 0.1 v dd v min v max absolute refin voltage limits 2 gnd ? 30 mv v min av dd + 30 mv v max average reference input current 400 na/v typ average reference input current drift 0.03 na/v/c typ normal mode rejection 2 same as for analog inputs common mode rejection same as for analog inputs excitation current sources (iexc1 and iexc2) output current 10/200/1000 a nom initial tolerance at 25c 5 % typ drift 200 ppm/c typ initial current matching at 25c 1 % typ matching between iexc1 and exc2. v out = 0 v drift matching 20 ppm/c typ line regulation (v dd ) 2.1 ppm/v max av dd = 5 v 5%. typically 1.25 ppm/v load regulation 0.3 ppm/v typ output compliance av dd ? 0.6 v max 10 a or 200 a currents selected av dd ? 1 v max 1 ma currents selected gnd ? 30 mv v min temp sensor accuracy tbd c typ bias voltage generator v bias av dd /2 v nom v bias generator start-up time tbd ms/nf typ depe ndent on the capacitance on the ain pin internal/external clock internal clock frequency 64 2% khz nom duty cycle 50:50 % typ drift 0.01 %/c typ external clock frequency 64 khz nom duty cycle 45:55 % typ logic inputs all inputs except sclk, din and clk 2 v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 2.0 v min dv dd = 3 v or 5 v sclk and din (schmi tt-triggered input) 2 v t (+) 1.4/2 v min/v max dv dd = 5 v v t (?) 0.8/1.4 v min/v max dv dd = 5 v v t (+) ? v t (?) 0.3/0.85 v min/v max dv dd = 5 v
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 5 parameter AD7792/ad7793b unit test conditions/comments v t (+) 0.9/2 v min/v max dv dd = 3 v v t (?) 0.4/1.1 v min/v max dv dd = 3 v v t (+) - v t (?) clk 2 v inl , input low voltage v inl , input low voltage v inh , input high voltage v inh , input high voltage input currents input capacitance 0.3/0.85 0.8 0.4 3.5 2.5 1 10 v min/v max v max v max v min v min a max pf typ dv dd = 3 v dv dd = 5 v dv dd = 3 v dv dd = 5 v dv dd = 3 v v in = dv dd or gnd all digital inputs logic outputs (including clk) v oh , output high voltage 2 dv dd ? 0.6 v min dv dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max dv dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min dv dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma (dout/ rdy )/800 a (clk) floating-state leakage current 1 a max floating-state output capa citance 10 pf typ data output coding offset binary system calibration 2 full-scale calibration limit zero-scale calibration limit input span 1.05 x fs -1.05 x fs 0.8 x fs 2.1 x fs v max v min v min v max power requirements 7 power supply voltage av dd ? gnd 2.7/5.25 v min/max dv dd ? gnd 2.7/5.25 v min/max power supply currents i dd current 150 a max 125 a typ, unbuffered mode, ext. reference 175 a max 150 a typ, buffered mode, in-amp bypassed, ext ref 380 a max 330 a typ, in-amp used, ext. ref 450 a max 400 a typ, in-amp used, int ref i dd (power-down mode) 1 a max 1 temperature range ?40c to +105c. 2 specification is not production tested but is supported by characterization data at initial product release. 3 following a self-calibration, this error will be in the order of the noise for the pr ogrammed gain and upda te rate selected. a system calibration will completely remove this error. 4 recalibration at any temperat ure will remove these errors. 5 full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (av dd = 4 v). 6 fs[3:0] are the four bits used in the mode register to select the output word rate. 7 digital inputs equal to dv dd or gnd.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 6 timing characteristics 4, 5 table 2. (av dd = 2.7 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted.) parameter limit at t min , t max (b version) unit conditionscomments t 3 100 ns min scl igh pulsewidth t 4 100 ns min scl low pulsewidth read operation t 1 0 ns min cs falling dge to doutrd active time 60 ns ma dv dd = 4.75 v to 5.25 v 80 ns ma dv dd = 2.7 v to 3.6 v t 2 6 0 ns min scl active dge to data valid dela 7 60 ns ma dv dd = 4.75 v to 5.25 v 80 ns ma dv dd = 2.7 v to 3.6 v t 5 8, 9 10 ns min bus relinuish time after cs inactive dge 80 ns ma t 6 100 ns ma scl inactive dge to cs inactive dge t 7 10 ns min scl inactive dge to doutrd igh rite operation t 8 0 ns min cs falling dge to scl active dge setup time 7 t 9 30 ns min data valid to scl dge setup time t 10 25 ns min data valid to scl dge old time t 11 0 ns min cs rising dge to scl dge old time 4 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10 to 90 of dv dd ) and timed from a voltage level of 1.6 v. 5 see figure 3 and figure 4. 6 these numbers are measured with the load circuit of figure 2 and defined as the time reuired for the output to cross the v ol or v o limits. 7 scl active edge is falling edge of scl. 8 these numbers are derived from the measured time taen b the data output to change 0.5 v when loaded with the circuit of figu re 2. the measured number is then etrapolated bac to remove the effects of charging or discharging the 50 pf capacitor. this means that the times uoted in the timing characteristics are the true bus relinuish times of the part and, as such, are independent of eternal bus loading capacitances. 9 rd returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read agai n, if reuired, while rd is high, although care should be taen to ensure that subseuent reads do not occur close to the net output update. in continuous read mode, the digital word can be read onl once.
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 7 +1.6 v 50 pf figure 2. load circuit for timing characterization t 2 t 3 t 4 t 1 t 6 t 5 t 7 04227-0-003 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb figure 3. read cycle timing diagram 04227-0-004 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 figure 4. write cycle timing diagram
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 8 absolute maximum ratings table 3. (t a = 25c, unless otherwise noted.) parameter rating av dd to gnd dv dd to gnd 0.3 v to 7 v 0.3 v to 7 v analog input voltage to gnd 0.3 v to av dd 0.3 v reference input voltage to gnd 0.3 v to av dd 0.3 v digital input voltage to gnd 0.3 v to av dd 0.3 v digital output voltage to gnd 0.3 v to av dd 0.3 v aindigital input current 10 ma operating temperature range 40c to 105c storage temperature range 65c to 150c maimum unction temperature 150c tssop a thermal impedance
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 9 pin configuration and fu nction descriptions 512 ain1(+) gnd 6 7 8 11 10 9 ain1(-) ain2(+) ain2(-) iout2 refin(-)/ain3(-) refin(+)/ain3(+) 3 4 14 13 cs iout1 dvdd avdd 1 2 16 15 sclk clk din dout/rdy AD7792/ ad7793 top view (not to scale) figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 scl serial cloc input for data transfers to and from the adc. the scl has a schmitttriggered input, maing the interface suitable for optoisolated applications. the serial cloc can be continuous wi th all data transmitted in a continuous train of pulses. alternativel, it can be a noncontinuous cloc with the information being trans mitted to or from the adc in smaller batches of data. 2 cl cloc incloc out. the internal cloc can be made availa ble at this pin. alternati vel, the internal cloc can be disabled and the adc can be driven b an eternal cloc. this allows several adcs to be driven from a common cloc, allowing simultaneous conversions to be performed. 3 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in sstems with more than one device on the serial bus or as a frame snchroniation signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3wire mode with scl, din, and dout used to interface with the device. 4 iout1 output of internal citation current source. the internal ecitation current source can be made available at this pin. the ecitation current source is programmable so that the current can be 10 ua, 200 ua or 1 ma. ither ixc1 or ixc2 can be switched to this output. 5 ain1() analog input. ai n1() is the positive terminal of the differe ntial analog input pair ain1()ain1(). 6 ain1() analog input. ain1() is th e negative terminal of the differential an alog input pair ain1()ain1(). 7 ain2() analog input. ain2 () is the positive terminal of the different ial analog input pair ain2()ain2(). 8 ain2() analog input. ain2() is th e negative terminal of the differential an alog input pair ain2()ain2(). 9 rfin()ain3() positive refe rence inputanalog input. an eternal reference can be applie d between rfin() and rfin(). r fin() can lie anwhere between av dd and gnd 0.1 v. the nominal reference voltage (rfin() rfin()) is 2.5 v, but the part functions with a reference from 0.1 v to av dd . alernativel, this pin can function as ain3() where ain3() is the positive terminal of the differential analog input pair ain3()ain3(). 10 rfin()ain3() negative re ference inputanalog input. rfin() is the negative reference input for rfin. th is reference input can lie anwhere between gnd and av dd 0.1 v. this pin also functions as ain3() which is the nega tive terminal of the differential analog input pair ain3()ain3(). 11 iout2 output of internal citation current source. the internal ecitation current source can be made available at this pin. the ecitation current source is programmable so that the current can be 10 ua, 200 ua or 1 ma. ither ixc1 or ixc2 can be switched to this output 12 gnd ground reference point. 13 av dd suppl voltage, 2.7 v to 5.25 v. 14 dv dd digital interface suppl voltage. the logic levels for the seri al interface pins are related to this suppl, which is between 2.7 v and 5.25 v. the d v dd voltage in independent of the voltage on av dd so, av dd can eual 3v with
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 10 pin no. mnemonic function d v dd at 5v or vice versa. 15 dout/rdy serial data output/data ready output. dout/rdy serves a dual purpose . it functions as a serial data output pin to access the output shift register of the adc. the output sh ift register can contain data from any of the on-chip data or control registers. in addition, dout/rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the da ta is not read after the conversion, the pin will go high before the next update occurs. the dout/rdy falling edge can be used as an interrupt to a pr ocessor, indicating that valid data is available. with an external serial clock, the data can be read using the dout/rdy pin. with cs low, the data/control word informa-tion is placed on the dout/rdy pin on the sclk falling edge and is valid on the sclk rising edge. the end of a conversion is also indicated by the rdy bit in the status register. when cs is high, the dout/rdy pin is three-stated but the rdy bit remains active. 16 din serial data input to the inp ut shift register on the adc. data in this shift register is transferred to the control registers within the adc, the register selection bits of the communications register identifying the appropriate register.
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 11 typical performance characteristics figure 6. figure 7. figure 8. figure 9. figure 10. figure 11.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 12 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described on the following pages. in the foll owing descriptions, set lesacstatead cleared lesacstatelesstersestated eccatsrestersatrtelresterllccatstteartststarttarteeratt tec catsresteredatarttetteccatsresterdetereseterteeteratsareadrrte erat adtcrestertserattaeslacerreadrrteeratscetesseetreadrrteeratt teselected resterscleteteteraceretrstereteectsarteerattteccatsresterssted ealtstate teteraceaderrateraresettestsdealtstateatrarteeratttecc atsres terstatsereteteraceseeceslstarteeratatleastseralclccclestret rstet tsdealtstateresettteetreartaletlestetdesatsrteccatsrestertr d catetetlcatdettetsareteccatsresterdetesterstttedatastrea eer racetsdcatesteerresetdealtstatstatt table 5. communications register bit designations bit location bit name description cr7 n rite nable bit. a 0 must be written to this bit so that the write to the communications register actuall occurs. if a 1 is the first bit written, the part will not cl oc on to subseuent bits in the register. it will sta at this bit location until a 0 is written to this bit. once a 0 is written to the n bit, the net seven bits will be loaded to the communications register. cr6 r a 0 in this bit location indicates that the net operati on will be a write to a specified register. a 1 in this position indicates that the net operation will be a read from the designated register. cr5cr3 rs2rs0 register address bits. these address bits are used to select which of the adcs registers are being selected during this serial interface communication. see table 6. cr2 crad continuous read of the data registe r. hen this bit is set to 1 (and th e data register is selected), the serial interface is configured so th at the data register can be continuo usl read, i.e., the contents of the data register are placed on the dout pin automati call when the scl pulses are applied. the commu nications register does not have to be written to fo r data reads. to enable continuous read mode, the instruction 01011100 must be written to the communica tions register. to eit the continuous read mode, the instruction 01011000 must be written to the communications register while the rd pin is low. hile in continuous read mode , the adc monitors activit on the di n line so that it can receive the instruction to eit continuous read mode. additionall, a reset will occur if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device. cr1cr0 0 these bits must be programmed to logic 0 for correct operation. table 6. register selection rs2 rs1 rs0 register register sie 0 0 0 communications register during a rite operation 8bit 0 0 0 status register during a read operation 8bit 0 0 1 mode register 16bit 0 1 0 configuration register 16bit 0 1 1 data register 16 24bit 1 0 0 id register 8bit 1 0 1 io register 8bit 1 1 0 offset register 16bit (AD7792)24bit (ad7793) 1 1 1 fullscale register 16bit (AD7792)24bit (ad7793)
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 13 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x80 (AD7792) / 0x88 (ad7793)) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communication s register, select the next operation to be a read, and load bits rs2, rs1 and rs0 with 0. table 7 outlines the bit designations for the st atus register. sr0 through sr7 indicate the bit locations, sr denoting the bits are in the status register. sr7 denotes the first bit of the d ata stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) 0(0) 0(0) 0/1 ch2(0) ch1(0) ch0(0) table 7. status register bit designations bit location bit name description sr7 rd read bit for adc. cleared when data is written to th e adc data register. the rd bit is set automaticall after the adc data register has been read or a period of time before the data re gister is updated with a new conversion result to indicate to the user not to read the conversi on data. it is also set when the part is placed in powerdown mode. the end of a conversion is indicated b the doutrd pin also. this pin can be used as an alternative to the status register for monitori ng the adc for conversion data. sr6 rr adc rror bit. this bit is written to at the same time as the rd bit. set to indicate that the result written to the adc data register has been clamped to al l 0s or all 1s. rror sources include overrange, underrange. cleared b a write operation to start a conversion. sr5sr4 0 these bits are automaticall cleared . sr3 01 this bit is automaticall cleared on the AD7792 and is automaticall set on the ad7793. sr2sr0 c2c0 these bits indicate which channel is being converted b the adc. mod rgistr (rs2, rs1, rs0 = 0, 0, 1; poronrst = 0000a) the mode register is a 16bit register from which data can be read or to which data can be written. this register is used to se lect the oper ating mode, update rate and cloc source. table 8 outlines the bit designations for the mode register. mr0 through mr15 indicat e the bit locations, mr denoting the bits are in the mode register. mr15 denotes the first bit of the data stream. the number in bracets indicates the poweronreset default status of that bit. an write to the setup register resets the modulator and filter and sets the rd bit. mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 md2(0) md1(0) md0(0) 0(0) 0(0) 0(0) 0(0) 0(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 cl1(0) cl0(0) 0(0) 0(0) fs3(1) fs2(0) fs1(1) fs0(0) table 8. mode register bit designations bit location bit name description mr15mr13 md2md0 mode select bits. these bits select the operational mode of the AD7792ad7793 (see table 9). mr12mr8 0 these bits must be programm ed with a logic 0 for correct operation. mr7mr6 cl1cl0 these bits are used to select the cloc source for the AD7792ad7793. ither on onchip 64 cloc can be used or an eternal cloc can be used. the abil it to override use an etern al cloc is useful as it allows several AD7792ad7793 devices to be snchronis ed. also, 50 60 is improved when an accurate eternal cloc drives the AD7792ad7793. cl1 cl0 adc cloc source 0 0 internal 64 cloc, internal cloc is not available at the cl pin 0 1 internal 64 cloc. this cloc is made available at the cl pin 1 0 ternal 64 cloc used. an ernal cloc gives better 50 60 reection. the eternal cloc can have a 4555 dut ccle. 1 1 ternal cloc used. this eternal cloc is divided b 2 within the AD7792ad7793. this allows the user to suppl a cloc whic h has a dut ccle worse than a 4555 dut ccle to the AD7792ad7793, for eample, a 128 cloc. mr5mr4 0 these bits must be programmed with a logic 0 for correct operation.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 14 bit location bit name description mr3-mr0 fs3-fs0 filter update ra te select bits (see table 10). table 9. operating modes md2 md1 md0 mode 0 0 0 continuous conversion mode (default). in continuous conversion mo de, the adc continuousl performs conversi ons and places the result in the data register. rd goes low when a conversion is complete. the user can read these conversions b placing the device in continuous read mode whereb the conversi ons are automaticall placed on the dout line when scl pulses are applied. alternativel, the user can inst ruct the adc to output the conversion b writing to the communications register. after poweron, a channel ch ange or a write to the mode, configuration or io registers, the first conversion is available after a period 2 f adc while subseuent conversions are available at a freuenc of f adc . 0 0 1 single conversion mode. in single conversion mode, the adc is placed in powerdown mode when conversions are not being performed. hen single conversion mode is selected, the adc powers up and performs a single conversion, which occurs after a period 2f adc . the conversion result in placed in the data register, rd goes low, and the adc returns to powerdown mode. the conversi on remains in the data register and rd remains active (low) until the data is read or another conversion is performed. 0 1 0 idle mode. in idle mode, the adc filter and modulator are held in a reset state although the modulator clocs are still provided 0 1 1 powerdown mode. in power down mode, all the AD7792ad7793 circuitr is powered down including the current sources, burnout currents, bias voltage generator and clout circuitr. 1 0 0 internal eroscale calibration. an internal short is automa ticall connected to the enabled channel. a calibration taes 2 conversion ccles to complete. rd goes high when the calibration is initia ted and returns low when the calibration is complete. the adc is placed in idle mode following a ca libration. the measured o ffset coefficient is placed in the offset register of the selected channel. 1 0 1 internal fullscale calibration. the fullscale input voltage is automaticall connected to the selected analog input for this calibration. the fullscale error of the AD7792ad7793 is calbrated at a gain of 1 using the internal reference in the factor. hen a channel is operated with a gain of 1 and the internal reference is selected, this factor calibrated value is loaded into the fullscale register wh en a fullscale calibration is initiated. hen the gain euals 1 and the eternal reference is selected, a cali bration taes 2 conversion ccles to complete. internal fullscale calibrations cannot be performed wh en the gain euals 128. ith this gain setting, a sstem fullscale calibration can be performed. for other gains, 4 conversion ccles are reuired to perform the fullscale calibration. rd goes high when the calibration is initiated and returns low when the ca libration is complete. the adc is placed in idle mode following a calibration. the measured fullscale coefficient is placed in the fullscale register of the selected channel. a fullscale calibration is reuired each time the gain of a channel is changed. 1 1 0 sstem offset calibration. user should connect the sstem eros cale input to the .channel input pins as selected b the c2c0 bits. a sstem offset calibration taes 2 co nversion ccles to complete. rd goes high when the calibration is initiated and returns low when the calibration is comp lete. the adc is placed in idle mode following a calibration. the measured offset co efficient is placed in the offset register of the selected channel. 1 1 1 sstem fullscale calibration. user should connect the sstem fullscale input to the .channel input pins as selected b the c2c0 bits. a calibration taes 2 conversion ccles to complete.. rd goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured fullscale coefficient is placed in the fullscale register of the selected channel. a fullscale calibration is reuired each time the gain of a channel is changed.
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 15 table 10. update rates available fs3 fs2 fs1 fs0 f adc () tsettle (ms) reection 50 60 (internal cloc) 0 0 0 0 0 0 0 1 500 5 0 0 1 0 250 8 0 0 1 1 125 16 0 1 0 0 62.5 32 0 1 0 1 50 40 0 1 1 0 41.6 48 0 1 1 1 33.3 60 1 0 0 0 19.6 101 90 db (60 onl) 1 0 0 1 16.6 120 84 db (50 onl) 1 0 1 0 16.6 120 70 db (50 and 60 ) 1 0 1 1 12.5 160 67 db (50 and 60 ) 1 1 0 0 10 200 69 db (50 and 60 ) 1 1 0 1 8.33 240 73 db (50 and 60 ) 1 1 1 0 6.25 320 74 db (50 and 60 ) 1 1 1 1 4.17 480 79 db (50 and 60 ) configuration rgistr (rs2, rs1, rs0 = 0, 1, 0; poronrst = 00710) the configuration register is a 16bit register from which data can be read or to which data can be written. this register is u sed to configure the adc for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana log input channel. table 11 outlines the bit designations for the filter register. con0 through con15 indicate the bit location s, con denoting the bits are in the configuration register. con15 denotes the first bit of the data stream. the number in bracets ind icates the poweronreset default status of that bit. con15 con14 con13 con12 co n11 con10 con9 con8 vbias1(0) vbias0(0) bo(0) ub (0) 0(0) g2(1) g1(1) g0(1) con7 con6 con5 con4 con3 con2 con1 con0 rfsl(0) 0(0) 0(0) buf(1) 0(0) c2(0) c1(0) c0(0) table 11. configuration register bit designations bit location bit name description con15con14 vbias1vbias0 bias voltage nable. the bias voltage generator a pplies a bias voltage of vdd2 to the selected negative analog input terminals. vbias1 vbias0 bias voltage 0 0 bias voltage generator disabled 0 1 bias voltage connected to ain1() 1 0 bias voltage connected to ain2() 1 1 reserved con13 bo burnout current nable bit. hen this bit is set to 1 b the use r, the 100 na current sources in the signal path are enabled. hen bo = 0, the bu rnout currents are disabled. the burnout currents can be enabled onl when the buffer or inamp is active. con12 ub unipolarbipolar bit. set b user to enable unipolar coding, i.e., ero differential input will result in 0000000 output and a fullscale differentia l input will result in 0ffffff output. cleared b the user to enable bipolar coding. negative fullscale di fferential input will result in an output code of 0000000, ero differential input will result in an output code of 0800000, and a positive full scale differential input will resu lt in an output code of 0ffffff. con11 0 this bit must be programmed with a logic 0 for correct operation. con10con8 g2g0 gain select bits.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 16 bit location bit name description written by the user to select the adc input range as follows g2 g1 g0 gain adc input range (2.5v reference) 0 0 0 1 (in-amp not used) 2.5 v 0 0 1 2 (in-amp not used) 1.25 v 0 1 0 4 625 mv 0 1 1 8 312.5 mv 1 0 0 16 156.2 mv 1 0 1 32 78.125 mv 1 1 0 64 39.06 mv 1 1 1 128 19.53 mv con7 refsel reference select bit. the referenc e source for the adc is selected using this bit. refsel reference source 0 external reference applied be tween refin(+) and refin(-) 1 internal reference selected con6 - con5 0 these bits must be progra mmed with a logic 0 for correct operation. con4 buf configures the adc for buffered or unbuffered mode of operation. if cleared , the adc operates in unbuffered mode, lowering the power consumption of the device. if set , the adc operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. the buffer can be disabled when the gain equa ls 1 or 2. for higher gains, the buffer is automaticallyenabled. con3 con2-con0 0 ch2-ch0 this bit must be programmed with a logic 0 for correct operation. channel select bits. written by the user to select the ac tive analog input channel to the adc. ch2 ch1 ch0 channel calibration pair 0 0 0 ain1(+) ? ain1(-) 0 0 0 1 ain2(+) ? ain2(-) 1 0 1 0 ain3(+) ? ain3(-) 2 0 1 1 ain1(-) ? ain1(-) 0 1 0 0 reserved 1 0 1 reserved 1 1 0 temp sensor automatically selects gain = 1 and internal reference 1 1 1 vdd monitor automatically selects gain = 1/6 and 1.17 v reference data rgistr (rs2, rs1, rs0 = 0, 1, 1; poronrst = 00000(00)) the conversion result from the adc is stored in this data register. this is a readonl register. on completion of a read opera tion from this register, the rd bitpin is set. id rgistr (rs2, rs1, rs0 = 1, 0, 0; po ronrst = 0xa (AD7792) 0xb (ad7793)) the identification number for the AD7792ad7793 is stored in the id re gister. this is a readonl register. io rgistr (rs2, rs1, rs0 = 1, 0, 1; poronrst = 000) the io register is an 8bit register from which data can be read or to which data can be written. this register is used to ena ble the ecitation currents and select the value of the ecitation currents. table 12 outlines the bit designations for the io register. io0 throu gh io7 indicate the bit locations, io denoting the bits are in the io register. io7 denotes the first bit of the data stream. the number in bra cets indicates the poweronreset default status of that bit.
preliminary technical data AD7792/ad7793 rev.prf 6/04 | page 17 io7 io6 io5 io4 io3 io2 io1 io0 0(0) 0(0) 0(0) 0(0) iexcdir1(0) iexcdir0(0) iexcen1(0) iexcen0(0) table 12 filter register bit designations bit location bit name description io7io4 0 these bits must be programmed with a logic 0 for correct operation. io3io2 ixcdir1 ixcdir0 direction of current sources select bits. ixcdir1 ixcdir0 current source direction 0 0 current source ixc1 connected to pin iout1, current source ixc2 connected to pin iout2 0 1 current source ixc1 connected to pin iout2, current source ixc2 connected to pin iout1 1 0 both current sources connected to pin iout1. permitted when the current sources are set to 10 ua or 200 ua onl. 1 1 both current sources connected to pin iout2. permitted when the current sources are set to 10 ua or 200 ua onl. io1io0 ixcn1 ixcn0 direction of current sources select bits. ixcn1 ixcn0 current source value 0 0 citation currents disabled 0 1 10 ua 1 0 200 ua 1 1 1 ma offst rgistr (rs2, rs1, rs0 = 1, 1, 0; poronrst = 0 8000(AD7792) 0800000(ad7793)) ach analog input channel has a dedicated offset register that holds the offset calibration coefficient for the channel. this register is 16 bits wide on the AD7792 and 24 bits wide on the ad7793 and, its poweronreset value is 8000(00) he. the offset register is u sed in con unction with its associated fullscale register to form a regi ster pair. the poweronreset value is automaticall overwritte n if an internal or sstem eroscale calibration is initiated b the user. the offset register is a readwrite register. owever, the AD7792 ad7793 must be in idle mode or power down mode when writing to the offset register. fullscal rgistr (rs2, rs1, rs0 = 1, 1, 1; poronrst = 05xx5(AD7792) 05xxxx5(ad7793)) the fullscale registers is a 16 bit register on the AD7792 and a 24bit register on the ad7793. the fullscale register holds the fullscale calibration coefficient for the adc. the AD7792ad7793 has 3 fullscale registers, each channel having a de dicated fullscale r egister. the fullscale registers are readwrite registers, owever, when writing to the fullscale registers, the adc must be placed i n power down mode or idle mode. these registers ar e configured on poweron with factorcali brated internal fullscale calibration coe fficients, the factor calibration being performed with the gain set to 1 an d using the internal reference. therefore, ever device will h ave different default coefficients. these default values are used when the device is operated with a gain of 1 and when the internal referenc e is selected. for other gains or when the eternal reference is used at a gain of 1, these default coefficients will be automaticall overwri tten if an internal or sstem fullscale calibration is initiated b the us er. a fullscale calibration should be performed when the gain is changed.
AD7792/ad7793 preliminary technical data rev.prf 6/04 | page 18 r r c thermocouple junction gnd av dd AD7792/ad7793 serial interface and control logic internal clock clk sigma delta adc ain1(+) ain1(-) ain2(+) ain2(-) mux in-amp refin(+) refin(-) bandgap reference gnd dout/rdy din sclk cs dv dd av dd gnd av dd iout2 v bias refin(+) refin(-) r ref figure 12. thermocouple a pplication using the AD7792/ad7793 gnd av dd AD7792/ad7793 serial interface and control logic internal clock clk s i g m a d e lta adc iout1 ain1(-) mux in-amp refin(+) refin(-) bandgap reference gnd dout/rdy din sclk cs dvdd av dd gnd iout2 refin(+) ain1(+) refin(-) rl1 rl2 rl3 rtd r ref figure 13. rtd application using the AD7792/ad7793

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